1. Field of the Invention
The present invention relates to a thin film transistor device having at least two kinds of thin film transistors, each having a gate insulating film, a thickness of which is different from that of the other, and to a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor device which can be applied to a liquid crystal display apparatus united with peripheral circuits and an organic EL display apparatus and to a method of manufacturing the same.
2. Description of the Prior Art
As display apparatuses of electronic instruments such as notebook type personal computers and portable terminals, a liquid crystal display panel and an organic electro luminescence (EL) display panel have been used. A plurality of pixels are arranged in horizontal and vertical directions in these display panels, and a desired image is displayed by controlling a voltage applied to each pixel. In an active matrix type liquid crystal display panel, one or a plurality of thin film transistors (TFTs) are provided for each pixel.
In recent years, development of a display panel united with peripheral circuits such as a driver (driving circuit), which are formed on a substrate thereof, has proceeded, and such products of the display panel have been put into practical use. Moreover, development of a so-called system-on-glass device, in which a memory, an image correction arithmetic circuit, and an arithmetic circuit having a high data processing function are formed on a display panel, has proceeded.
FIG. 1 is a section view showing an example of a TFT (n-type) used for a conventional liquid crystal display apparatus united with a peripheral circuit.
An underlayer insulating film 11 made of a silicon oxide film or the like is formed on a substrate 10, and a polysilicon film 12 serving as an operational layer of the TFT is selectively formed on the underlayer insulating film 11. In the polysilicon film 12, a pair of high concentration impurity regions (source/drain) 13 formed by doping n-type impurities thereinto at a high concentration are formed so as to sandwich a channel region therebetween. In tip portions of these high concentration impurity regions 13 closer to the channel region, low concentration impurity regions, lightly doped drain (hereinafter referred to as LDD region) 14, which are formed by doping n-type impurities thereinto at a low concentration, are respectively formed.
A gate insulating film 15 made of a silicon oxide film or the like is formed on the underlayer insulating film 11 and the polysilcon film 12, and a gate electrode 16 is formed on the gate insulating film 15. Moreover, an interlayer insulating film 17 made of a silicon oxide film or the like is formed on the gate insulating film 15 and the gate electrode 16.
Electrodes (source electrode and drain electrode) 18 are formed on the interlayer insulating film 17. These electrodes 18 are electrically connected to the respective high concentration impurity regions 13 via contact holes formed in the interlayer insulating film 17 and the gate insulating film 15.
As shown in FIG. 1, in order to suppress deterioration of an ON characteristic due to hot carriers and to decrease an OFF current, the TET of the liquid crystal display apparatus united with peripheral circuits generally has an LDD structure, in which the low concentration impurity regions 14 are formed in the tip portions of the high concentration impurity regions 13 closer to the channel region. When viewed from above, an edge of each low concentration impurity region 14 is located approximately just below the gate electrode 16. Note that the portions corresponding to the low concentration impurity regions 14 may be used also as an offset region without doping the impurities into those portions.
FIGS. 2A and 2B are section views showing other examples of conventional TFTs. FIG. 2A shows a structure of a low-voltage driven TFT, and FIG. 2B shows a structure of a high-voltage driven TFT. These low and high-voltage driven TFTs are formed on the same substrate 20.
An underlayer insulating film 21 is formed on the substrate 20, and a polysilicon film 22 serving as an operational layer of the TFT is formed on the underlayer insulating film 21. The underlayer insulating film 21 is made of, for example, a silicon oxide film (SiO2), and has a thickness of about 80 nm. Moreover, a thickness of the polysilicon film 22 is about 50 nm.
As shown in FIG. 2A, a pair of high concentration impurity regions 23 serving as a source/drain are formed in the polysilicon film 22 of the low-voltage driven TFT so as to sandwich a channel region. A thin gate insulating film 25a is formed on the channel region of the low-voltage driven TFT, which is formed in the polysilicon film 22, and a gate electrode 26a is formed on the gate insulating film 25a. The gate insulating film 25a is made of, for example, a silicon oxide film, and has a thickness of about 30 nm.
On the other hand, as shown in FIG. 2B, in a polysilicon film 22 of the high-voltage driven TFT, a pair of high concentration impurity regions 23 are formed so as to sandwich a channel region. Moreover, in this polysilicon film 22, low concentration impurity regions (LDD regions) 24 are formed so that each is located between the respective high concentration impurity regions 23 and the channel region. A thick gate insulating film 25b is formed on the channel region and the low concentration impurity regions 24 in the polysilcon film of the high-voltage driven TFT, and a gate electrode 26b is formed on the gate insulating film 25b. The gate insulating film 25b is made of, for example, a silicon oxide film, and has a thickness of about 130 nm. Moreover, the gate electrodes 26a and 26b of the low and high-voltage driven TFTs are made of, for example, Cr (chromium), and have a thickness of about 400 nm.
The polysilicon film 22 and the gate electrodes 26a and 26b are covered with an interlayer insulating film 27 made of a silicon nitride film (SiN) or the like. A thickness of the interlayer insulating film is, for example, 300 nm. Electrodes (source electrodes and drain electrodes) 28, which are electrically connected to the respective high concentration impurity regions 23 via contact holes formed in the interlayer insulating film 27, are formed on the interlayer insulating film 27.
Since the low-voltage driven TFT shown in FIG. 2A has a thin gate insulating film and no LDD region showing a high resistivity, this TFT can perform a high speed operation with a low voltage. Since the high-voltage driven TFT shown in FIG. 20 has a thick gate insulating film and the low concentration impurity regions (LDD region) 24 provided therein, which prevent occurrence of hot carriers, this TFT can prevent deterioration of characteristics even when ibis TFT is driven with a high voltage.
In Japanese Patent Laid-open No. 10(1998)-27909, No. 10(1998)-170953, No. 5(1993)-142571 and No. 7(1995)-249766, technologies for forming transistors having gate insulating films of different thickness in the same semiconductor substrate are disclosed.
In Japanese Patent Laid-open No. 8(1996)-220505, a technology is proposed, in which of a high and low-voltage driven transistors used for a liquid crystal display apparatus, only the high-voltage driven transistor is constructed of an LDD structure.
The inventors of this application consider that there are the following problems in the above described conventional thin film transistor device.
Since the TFT shown in FIG. 1 has the LDD structure, this TFT can suppress deterioration of characteristics due to hot carriers. An ON characteristic is restricted by a resistivity of the low concentration impurity regions (LDD layer) 14. Therefore, a high speed operation of the TFT is disturbed, thus producing obstacles in incorporating high function circuits such as an image data memory and an image processing arithmetic circuit, of which a high speed operation is required, into a display panel.
In the TFT shown in FIG. 2A, the thickness of the gate insulating film 25a is small, and the gate insulating film 25a is formed so as to have the same width as that of the electrode 26a. Accordingly, a gap between the gate electrode 26a and the source/drain (high concentration impurity region 23) is very small. Impurities, contaminant ions and the like adhere to a side wall of the gate insulating film 25a in a step such as etching, and a leak current is apt to occur when a gap between the gate electrode 26a and the source/drain is small.
When the conventional low and high-voltage driven TFTs shown in FIGS. 2A and 2B are formed on the same substrate, the gate insulating film 25a and the gate electrode 26a of the low-voltage driven TFT are formed, and then the gate insulating film 25b and the gate electrode 26b of the high-voltage driven TFT are formed. In this case, a surface of the polysilicon film 22 is treated by solution containing hydrofluoric acid to purify an interface between the polysilicon film 22 and the gate insulating film 25b. At this time, the gate insulating film 25a of the low-voltage driven TFT is corroded by the hydrofluoric acid solution, and the leak current is more apt to occur.